// -------------------------------------------------------------
//    Copyright 2013 Synopsys, Inc.
//    All Rights Reserved Worldwide
// 
//    Licensed under the Apache License, Version 2.0 (the
//    "License"); you may not use this file except in
//    compliance with the License.  You may obtain a copy of
//    the License at
// 
//        http://www.apache.org/licenses/LICENSE-2.0
// 
//    Unless required by applicable law or agreed to in
//    writing, software distributed under the License is
//    distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
//    CONDITIONS OF ANY KIND, either express or implied.  See
//    the License for the specific language governing
//    permissions and limitations under t,he License.
// -------------------------------------------------------------
// 
interface dut_if(input bit clk,input bit rst);

 logic [7:0] wdata;
 logic [7:0] rdata;
 logic [31:0] addr;
 logic direction;
 logic enable;
  
 clocking cb @(posedge clk);
   output wdata;
   output addr;
   output direction;
   output enable;
   input  rdata;
 endclocking

 modport mst(clocking cb);
endinterface

